1. Field of the Invention
Embodiments of the present disclosure relate to semiconductor memory devices and semiconductor systems including the same.
2. Description of the Related Art
In general, semiconductor memory devices may include a plurality of memory cells. As the semiconductor memory devices become more highly integrated, the number of the memory cells in each of the semiconductor memory devices has been rapidly increased. Each of the semiconductor memory devices including the memory cells may execute a read operation and/or a write operation in response to control signals provided from a controller to store (or write) input data in the memory cells and/or to output (or read) the data stored in the memory cells.
Meanwhile, as the operation speed of semiconductor systems including the semiconductor memory devices and the controllers get faster, it has become more and more important to control or adjust the timing between a command signal, an address signal and data that the controller applies to semiconductor memory devices. That is, the timing between various output signals of the controller has to be accurately controlled for reliable and accurate operations of the semiconductor systems. In particular, as the transmission speed (e.g., input and output speeds) of the data become faster, it may be necessary to accurately find out delay times of the data on channels between the controller and the semiconductor memory device. Finding out information (e.g., the delay times) on the channels through which the data are transmitted is referred to as “channel training”.
Referring to FIG. 1, a first output data DOUT<1> has stable levels at rising edges “T1” and “T3” and falling edges “T2” and “T4” of a clock signal CLK without any level transitions. Thus, no data errors occur in the first output data DOUT<1>.
In contrast, a level of a second output data DOUT<2> changes at the rising edges “T1” and “T3” and the falling edges “T2” and “T4” of the clock signal CLK. Thus, data errors may occur in the second output data DOUT<2>.
Similarly, a level of a third output data DOUT<3> changes at the rising edges “T1” and “T3” and the falling edges “T2” and “T4” of the clock signal CLK. Thus, data errors may also occur in the third output data DOUT<3>.
According to FIG. 1, if the first output data DOUT<1> has a normal delay time, the second output data DOUT<2> may have an abnormal delay time which is greater than the normal delay time and the third output data DOUT<3> may have an abnormal delay time which is less than the normal delay time.
If a delay time of data changes due to process/voltage/temperature (PVT) conditions, levels of the data may change at rising edges and falling edges of a clock signal. In such a case, data errors may occur to degrade the reliability of the data.